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SPEAR-2 (24245)
Rationale
The emerging advanced communications systems require high-performance computing embedded devices in order to support new features such as real-time speech recognition, video or image/data compression. As an example the half rate GSM protocol requires an overall computing power of 40 millions operations per second. In these new systems, such special-purpose devices (DSPs), or co-processors, frequently act in conjunction with microcontrollers. However due to the increasing application complexity, and to the system constraints, the reduction of components is an important issue regarding the system cost. SPARClet 2 is a general purpose and modular architecture combining digital signal functions, superscalar techniques and on-chip peripherals, specially designed to address these requirements.
Objectives
The objectives of this 8 month project is to realize a feasibility study on a cost effective version of the SPARClet architecture dedicated to broadcast media embedded applications. In order to reach an expected 200 mips performance level requirement, architecture innovations will be investigated, such as superscalar execution and non-blocking caches. This architecture will be the foundation for a new family of embedded processors.
A "C" compiler will be drafted, after state-of-the-art technology evaluation, in order to optimize the code generation for this architecture, and to propose a software development tool to the customers of the SPARClet II.
A market survey will lead to the first SPARClet II based product definition. A business model, coupled with a business plan will be proposed for this product, with explanations on the return-on-investment hypothesis. The major success criteria will be a positive conclusion on the feasibility study, which will pave the way for a project dedicated to the realization and validation of a SPARClet II product.
Approach
The feasibility study will be based on the background coming from the SPARClet architecture for T.Sqware. The project will focus on t he SPARClet architecture improvement. The objective of 200 mips can not be achieved only through a technology shrink from 0.5 micron to 0.35 micron which allows a clock frequency of 100 mhz. Architectural innovations such as superscalar execution and non-blocking caches must be used.
The architecture will also have DSP capabilities through implementation of specific instructions, parallel execution units and out-of-order execution while keeping compatible with the SPARC standard. Special attention will be given to market analysis, using the standard qualitative parameters, and extrapolating from new customers trends and the expected behaviour of the broadcast media market over the next years.
In order to fit with the SPARClet II architecture, from the performance as well as from the user-friendliness point of view, a compiler will be defined at draft level, with special code optimization.
Exploitation
T.SQWAREand ACE will transform the feasibility study into products in a short time cycle, based on the assumption that a continuation consortium will be formed to implement and validate the product defined during this project. However, even as a feasibility project, there is an exploitation value all by itself in the following way:
The technology defined in this project will be used to quickly derive different products tailored for some specific markets in the broadcast media domain. The "C" compiler will be marketed by T.SQWARE and ACE as the tool of choice for developing software using the best of the SPARClet II architecture.
Start date: November 1997
End date: June 1998
Project Coordinator:
Dan Abiker
T.SQWARE
Parc Arlane, Immeuble Mercure 6
78284 Yvelines Guyancourt Cedex
France
Tel: 0033-1-39442915
Fax: 0033-1-39442930
Email: dan.abiker@tsquare.fr
Partners:
MATRA MHS (France) ... now T.SQWARE (France)
IRISA / INRIA (Institut National de Recherce en Informatique et en Automatique ) (France)
FORTH (Greece)
ACE Compiler experts (The netherlands)