CORDIS Archive

PEOPLE (26796)

Compared to today's 0.35µm technology, the power dissipation of a device will increase in the next three years by a factor of more than seven. Power dissipation will clearly become the limit-ing constraint of high performance devices. This holds even under the consideration of signifi-cantly reduced power supply voltages. Practical considerations and market demands for mobile communication and computing impose the need for significant power reduction. The technology advancements of integrated circuits require significant changes in the design practice:

• Layout driven synthesis to fully utilize the performance provided by the technology.
• System level design based on re-use to enable the design of systems on chip.
• Design for low power at all levels of abstraction to utilize the full chip size available for the implementation of the necessary functionality.

Since power consumption has become a critical issue in the development of any digital system, tools that allow one to control the power budget during the various phases of the development process are in high demand. Given an initial, system-level specification of the design, several partitioning/synthesis/ optimization steps are required to generate a power-efficient architecture which meets the constraints posed at the specification stage.

The objective of this project is the development of a tool-suite for fast, yet accurate power estimation of designs starting at a very high level of abstraction down to the implementation level.

In order to achieve the abstract objectives of this proposal, a concrete design flow shall be de-veloped which supports an early, efficient and sufficiently accurate design space exploration. The design flow will be developed according to the following principles:

• User driveness, i.e. the requirements and scope of the technical developments are defined driven by the industrial participants;
• Use of standards, i.e. where ever applicable standards will be used in preference to own de-velopments;
• Utilization of commercial tools where ever possible in preference to own developments;
• Early feed back from real applications, i.e. at early phases of the tool development, users will evaluate intermediate results and the user feed back will be used to adapt the work plan and technical developments.

In view of these principles the new design flow will interface to industry standard back end design flow. It will be based on standard HDLs, i.e. VHDL. Furthermore for design optimization the project relies on the availability of commercial high level synthesis tools.

The tools and design methodologies to be developed will be embedded in a unified user interface with access to a common data base. The result will be evaluated with industrial designs. The complete system will be marketed as a commercial product and service.

To achieve the goal, a consortium with well-recognized background and specific competence on the subject of high-level power estimation has been put together. The two research institutions, OFFIS and Polito, have a widely-established tradition in methods and tools for HW/SW co-design and low-power design for digital systems. LEDA, on the other hand, owns expertise on the development of commercial computer-aided design tools for VHDL-based designs. ARM is the technology provider in this project. Finally two of the main European Telecommunication Companies (Alcatel and Italtel) joined the Consortium to contribute with their industrial experience in designing complex systems.

Start date: April 1998
End date: December 2000

Project Coordinator:

Francis Sourbier
Leda Languages for Design Automation S.A
Avenue du Granier 35
38240 Meylan
France
Tel: 0033 4 76 41 92 43
fax: 0033 4 76 41 92 44
Email: sourbier@leda.fr

Project Contact:

Kuratorium OFFIS e.V.
R&D Division Embedded Systems
Escherweg 2
26121 Oldenburg
Germany
Tel: 0049-441-9722 0
Fax: 0049-441-9722 102

Partners:

Alcatel (Germany)
Advanced Risc Machines (United Kingdom)
Italtel (Italy)
Leda Languages (France)
OFFIS (Germany)
Politecnico di Torino (Torino, Italy)