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Multi-coRe, multi-level, WDM-enAbled embedded optical enGine for Terabit board-to-board and rack-to-rack parallel optics

Project description


Core and disruptive photonic technologies
MIRAGE aims to implement cost-optimized components for terabit optical interconnects introducing new multiplexing concepts through the development of a flexible, future-proof 3D "optical engine".
Data centers are becoming the hot spots of internet, and content providers request a technology for practical and cost-effective upgrade to Tb/s capacities. MIRAGE is an industry-driven photonic integration project that aims to provide this technology and present a viable path to scale datarate (+640%), power (-70%) and no. of fibres (-90%) by squeezing bulk parallel optical components into 3D integrated chips. MIRAGE will introduce new dimensions of parallelization in interconnects to gracefully upgrade capacity and density combining for the first time multi-core fiber multiplexing, coarse WDM multiplexing and multi-level modulation. To address cost, performance and volume MIRAGE relies on the strengths of Si photonics and electronics and extends it using the right synergies with established photonic integration materials (InP and glass) to provide a future-proof, upgradeable technology. MIRAGE optical board will provide efficient (2dB) vertical coupling for photonic 3D integration and compact wavelength multiplexing on 8” Si wafers. MIRAGE will exploit the efficiency of VCSEL technology to develop the first SOI-compatible 40Gb/s InP VCSELs at 1550nm and will upgrade them to 80Gb/s through simple multi-level modulation. To further address parallelization, MIRAGE will integrate the InP VCSELs in monolithic WDM arrays. Leveraging advances in single-mode multicore fiber MIRAGE aims to mitigate cabling cost and size and reduce chip area for pigtailing by developing low-cost glass multi-core interfaces with simple assembly on the SOI chip. 4-element silicon TIA and VCSEL driver arrays will be implemented for 40 Gbaud multi-level modulation. Low-cost industry-compatible 3D assembly techniques will be optimized for high-speed electro-optic chips, bringing a >50-fold improvement in electrical vias capacitance. MIRAGE will deliver fully functional 3D PICs: a) 208 Gb/s board-level interconnect b) 320 Gb/s QSFP active optical cable (AOC) c) 960 Gb/s CXP AOC with QSFP breakout.

Data centers are becoming the hot spots of internet, and content providers request a technology for practical and cost-effective upgrade to Tb/s capacities. MIRAGE is an industry-driven photonic integration project that aims to provide this technology and present a viable path to scale datarate (+640%), power (-70%) and no. of fibrer (-90%) by squeezing bulk parallel optical components into 3D integrated chips. MIRAGE will introduce new dimensions of parallelization in interconnects to gracefully upgrade capacity and density combining for the first time multi-core fiber multiplexing, coarse WDM multiplexing and multi-level modulation. To address cost, performance and volume MIRAGE relies on the strengths of Si photonics and electronics and extends it using the right synergies with established photonic integration materials (InP and glass) to provide a future-proof, upgradeable technology. MIRAGE optical board will provide efficient (2dB) vertical coupling for photonic 3D integration and compact wavelength multiplexing on 8" Si wafers. MIRAGE will exploit the efficiency of VCSEL technology to develop the first SOI-compatible 40Gb/s InP VCSELs at 1550nm and will upgrade them to 80Gb/s through simple multi-level modulation. To further address parallelization, MIRAGE will integrate the InP VCSELs in monolithic WDM arrays. Leveraging advances in single-mode multicore fiber MIRAGE aims to mitigate cabling cost and size and reduce chip area for pigtailing by developing low-cost glass multi-core interfaces with simple assembly on the SOI chip. 4-element silicon TIA and VCSEL driver arrays will be implementedfor 40 Gbaud multi-level modulation. Low-cost industry-compatible 3D assembly techniques will be optimized for high-speed electro-optic chips, bringing a >50-fold improvement in electrical vias capacitance. MIRAGE will deliver fully functional 3D PICs: a) 208 Gb/s board-level interconnect b) 320 Gb/s QSFP active optical cable (AOC) c) 960 Gb/s CXP AOC with QSFP breakout.

Call for proposal

FP7-ICT-2011-8
See other projects for this call

Coordinator

EREVNITIKO PANEPISTIMIAKO INSTITOUTO SYSTIMATON EPIKOINONION KAI YPOLOGISTON
EU contribution
€ 447 398,00
Address
Patision 42
106 82 Athina
Greece

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Region
Αττική Aττική Κεντρικός Τομέας Αθηνών
Activity type
Research Organisations
Administrative Contact
Hercules Avramopoulos (Prof.)
Links
Total cost
No data

Participants (7)