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Formal design methods for globally asynchronous/locally synchronous embedded computing systems

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Boosting computing systems' productivity

A gap exists between the design and productivity of complex and heterogeneous embedded computing systems. A European project is looking to close this gap through a set of formal methods and programming languages developed over 24 months.

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Heterogeneous computing systems are basically electronic systems that run different computational units (such as audio or video systems, networked applications, etc.) and need extra specialised resources to work. The design-productivity gap in these systems occurs for two main reasons: embedded processors are becoming more complex and the applications running on these processors are larger and equally complex. As a result, the DynaGALS project looked at three issues to overcome these problems: high-level programming languages, time-predictability, and component-based design. To tackle the first concern, the researchers looked at the SystemJ programming language. SystemJ is particularly suited to the design of globally asynchronous locally synchronous systems (GALS), a crucial part of the project. DynaGALS set about defining the task and conducted case studies to see whether SystemJ could be used for the design of embedded computing systems. Secondly, the team created a new time-predictive programming language, called Precision Timed C (Pret_C). This is based on the widely used C programming language with some added dynamics to improve performance. Pret C allows memory communication between two existing threads, something normal C programming does not offer. As a result, the mapping of logical time to physical time was more easily achieved. Arpret, a dedicated target architecture combining a hardware accelerator with a soft core processor which increased the efficiency of Pret_C, was also designed. The third issue that DynaGALS tackled had to do with component-based systems. These are complex systems that are made of blocks of code or components. An essential problem is how to compose components designed in isolation when only the communication interface of an individual component is known. When you try to link the different components together, regular mismatches occur. As a result, the team created a new formal approach incorporating a converter synthesis (a type of verification) which bridged the mismatches between different components. The project, which cost EUR 111,667, ran until February 2010. SystemJ promises to become the major system-level design language for complex and heterogeneous embedded systems.

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