3C-SiC Hetero-epitaxiALLy grown on silicon compliancE substrates and 3C-SiC substrates for sustaiNable wide-band-Gap powEr devices

Informations projet

CHALLENGE

N° de convention de subvention: 720827

DOI

10.3030/720827

Projet clôturé

Date de signature de la CE 9 Novembre 2016

Date de début 1 Janvier 2017

Date de fin 30 Juin 2021

Financé au titre de

• INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Advanced materials

Coût total

€ 8 048 322,50

Contribution de l’UE

€ 7 997 822,50

Coordonné par

CONSIGLIO NAZIONALE DELLE RICERCHE
Italy

Periodic Reporting for period 3 - CHALLENGE (3C-SiC Hetero-epitaxiALLy grown on silicon compliancE substrates and 3C-SiC substrates for sustaiNable wide-band-Gap powEr devices)

Période du rapport: 2020-01-01 au 2021-06-30

Résumé du contexte et des objectifs généraux du projet

We propose a new approach to improve the quality and to reduce stress: it is necessary to modify the structure of the substrate (compliance substrate) in order to force the system to reduce the defects while increasing the thickness of the layer.

Furthermore, by using the typical bulk growth techniques used for 4H-SiC it is possible to grow bulk 3C-SiC wafers, improving considerably the quality of the material.

Currently silicon is the material of choice for power electronic applications where the inevitable power dissipation requires the use of very heavy and expensive heat sinks. The purpose of these undesirable heat sinks is to manage the device junction temperature, allowing operation in the range where Si devices are able to function. The reason is simple - the low Si band-gap.

The best alternative for these applications is 3C-SiC.

Travail effectué depuis le début du projet jusqu’à la fin de la période considérée dans le rapport et principaux résultats atteints jusqu’à présent

In this first eighteen months of the project the activity has been concentrated essentially on the development of the compliance substrates, on the hetero-epitaxial and bulk growth. Several defects (voids, protrusions, stacking faults, …) have been studied in detail by different experimental techniques, to try to improve the quality of the material. Some effort has been used to try to understand and reduce the stress in the grown layer and the final bow. The effect of different compliance substrates on the substrate bow has been also analysed in detail with the comparison between experimental and simulation results. Also the development of the processing (metallization, gate oxidation, ion implantation, …) necessary for the realization of the devices has started in the last part of the first year.
Some interesting results have been obtained in the reduction of voids at the 3C-SiC/Si interface, the reduction of protrusions both in hetero-epitaxial growth and in bulk growth, in the understanding of SFs behaviour and in the reduction of this kind of defects in bulk growth. Also the modelling of stress in compliance substrates has given new understanding on the growth process.

Progrès au-delà de l’état des connaissances et impact potentiel prévu (y compris l’impact socio-économique et les conséquences sociétales plus larges du projet jusqu’à présent)

The samples for evaluation have been fabricated. Then, defect density, internal stress, and configuration of structural defect will be revealed till end of October. The fine-tuning of 3C-SiC growth condition will be carried out referring the evaluation results. Finally, the defect density will be reduced below 100/cm keeping the internal stress lower than 200MPa.

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