Periodic Reporting for period 2 - PlasmoniAC (Energy- and Size-efficient Ultra-fast Plasmonic Circuits for Neuromorphic Computing Architectures)
Período documentado: 2021-07-01 hasta 2023-09-30
The explosive growth and effectiveness of Deep Learning (DL) algorithms comes at a cost of increasing scale, computational power and energy requirements. Already, acclaimed DL models like ChatGPT-3, are reaching daily power consumptions of up to 11 TWh, with future forecasts projecting doubling of the computing power requirements every 5-6 months. The way to the rescue was initially sought in innovative electronic AI hardware architectures, including neuromorphic and analog-in-Memory Computing (AiMC), where however the achieved efficiencies are inherently limited due to the speed and power limits of the underlying electronic interconnects. This deadlock has driven the emergence of a new field of custom DL hardware, i.e photonic accelerators, which aims to transfer the well-known high-bandwidth and low-energy interconnect credentials of photonic circuitry in the area of DL platforms.
Inspired by this new computing paradigm, PlasmoniAC aimed to harmonically synergize the best-in-class material platforms and photonic accelerator architectures with a novel DL framework that incorporates the idiosyncrasy of the underlying photonic components into Neural Network (NN) training. This unique proposition allowed PlasmoniAC prototypes to breach the energy/footprint efficiency barriers of currently available electronic accelerators and offer unprecedented energy efficiencies down to 86 fJ/MAC while supporting baud rates > 50 Gbaud. Moreover, driven by real application needs, the developed platform was used as a computational substrate for a variety of workloads in the areas of image identification, cybersecurity threat detection and optical channel equalization.
Inspired by this new computing paradigm, PlasmoniAC aimed to harmonically synergize the best-in-class material platforms and photonic accelerator architectures with a novel DL framework that incorporates the idiosyncrasy of the underlying photonic components into Neural Network (NN) training. This unique proposition allowed PlasmoniAC prototypes to breach the energy/footprint efficiency barriers of currently available electronic accelerators and offer unprecedented energy efficiencies down to 86 fJ/MAC while supporting baud rates > 50 Gbaud. Moreover, driven by real application needs, the developed platform was used as a computational substrate for a variety of workloads in the areas of image identification, cybersecurity threat detection and optical channel equalization.
During the project, the consortium has focused on four core action lines to meet its technical objectives.
Developing and merging the best-in-class material technologies in a single PIC computational platform. PlasmoniAC investigated novel plasmonic and non plasmonic materials including (i) BTO, POH and TiO2 for its input data and weight modulation technology. Through executing a meticulous workplan, PlasmoniAC deployed novel BTO-on-SiN modulators operating at up to 128 GBaud with a voltage-length product of 4.2 Vmm, while the work on TiO2-based weighting modules concluded to a low Pπ of 25 mW (ii) Graphene, InP and SiGe for developing photodetection and non-linear activation circuitry. To this end, PlasmoniAC investigated novel zero-bias graphene photodetectors with theoretical responsivities of 1 A/W, while also deploying a new-class of opto-electronic and all-optical activation circuitry. This included, a SiGe BICMOS electronic circuity operating both as a pre-amplifier and a programmable activation function module up to 10 Gbaud, and a InP micro-disk nano laser operating as an all-optical activation function with input powers as low as 11.5 uW. (iv) HfO2 based memristive elements for non-volatile weighting, demonstrating the first photonic weighting structure controlled through a memristive element. (v) SiN for deploying a loss optimized interconnect substrate for synergizing its best-in class materials.
Design and deploy optimized photonic accelerator architectures. Through its execution, PlasmoniAC evolved its GA envisioned coherent linear neuron architecture into a fully-fledged Photonic Xbar design, drawing inspiration from the success of electronic XBar arrays. This development allowed PlasmoniAC to further its initial trainable parameter targets and highlighted a pathway towards high-scale, high-weight update accelerators.
From its conception PlasmoniAC aimed to bridge the gap between the currently deployed rigid DL framework with the idiosyncrasy of the underlying analog photonic components, a far cry of the mature and predictable digital counterparts. This vision allowed PlasmoniAC to develop a new DL framework, capable of integrating in the NN training the performance degrading factors of photonic accelerators. This framework was successfully deployed in both software models of PNNs and experimentally validated in PlasmoniAC prototypes, revealing significant accuracy and or bandwidth relaxation benefits. Finally, PlasmoniAC successfully merged its innovative DL framework with an established photonic circuitry simulation suite (VPI), migrating its models and algorithms in a powerful VPI-PyTorch co-simulation suite.
Prototyping and application benchmarking. In view of both safeguarding the deployment of PlasmoniAC’s photonic architectures in tangible integrated prototypes and benchmarking its architectures in different plasmo-photonic integration platforms, PlasmoniAC laid out a four-folded development roadmap that encompassed the development of four generations of photonic accelerator prototypes, that concluded to a 4x4 Xbar prototype using SiGe EAM for up to 50 Gbaud operation and a POH-based design that will include Phase Change Materials. Finally, PlasmoniAC assessed the performance of its fabricated prototypes through the experimental deployment of a wide range of DL datasets for: (i) image recognition e.g. MNIST, CIFAR-10, (ii) application specific NN-classifiers for cybersecurity network traffic monitoring i.e. DDOS reconnaissance attack identification and optical communication i.e. NN-assisted channel equalization.
Activities related to the development and integration of the BTO modulators and graphene PDs led to the founding of two start-up companies by IBM and AMO respectively. In addition, AUTH’s and MLNX (NVIDIA)’s pioneering work in the fields of photonic accelerators and network cybersecurity led to 4 US patents.
The multi-disciplinary research of PlasmoniAC has led to over 20 journal articles and appearance in 50 conferences proceedings including 20 invited talks. Finally, PlasmoniAC successfully co-organized two workshops in “Neuromorphic Photonics”, that attracted worldwide attention from both academia and industry while also promoting collaboration between relevant EU Horizon programs.
Developing and merging the best-in-class material technologies in a single PIC computational platform. PlasmoniAC investigated novel plasmonic and non plasmonic materials including (i) BTO, POH and TiO2 for its input data and weight modulation technology. Through executing a meticulous workplan, PlasmoniAC deployed novel BTO-on-SiN modulators operating at up to 128 GBaud with a voltage-length product of 4.2 Vmm, while the work on TiO2-based weighting modules concluded to a low Pπ of 25 mW (ii) Graphene, InP and SiGe for developing photodetection and non-linear activation circuitry. To this end, PlasmoniAC investigated novel zero-bias graphene photodetectors with theoretical responsivities of 1 A/W, while also deploying a new-class of opto-electronic and all-optical activation circuitry. This included, a SiGe BICMOS electronic circuity operating both as a pre-amplifier and a programmable activation function module up to 10 Gbaud, and a InP micro-disk nano laser operating as an all-optical activation function with input powers as low as 11.5 uW. (iv) HfO2 based memristive elements for non-volatile weighting, demonstrating the first photonic weighting structure controlled through a memristive element. (v) SiN for deploying a loss optimized interconnect substrate for synergizing its best-in class materials.
Design and deploy optimized photonic accelerator architectures. Through its execution, PlasmoniAC evolved its GA envisioned coherent linear neuron architecture into a fully-fledged Photonic Xbar design, drawing inspiration from the success of electronic XBar arrays. This development allowed PlasmoniAC to further its initial trainable parameter targets and highlighted a pathway towards high-scale, high-weight update accelerators.
From its conception PlasmoniAC aimed to bridge the gap between the currently deployed rigid DL framework with the idiosyncrasy of the underlying analog photonic components, a far cry of the mature and predictable digital counterparts. This vision allowed PlasmoniAC to develop a new DL framework, capable of integrating in the NN training the performance degrading factors of photonic accelerators. This framework was successfully deployed in both software models of PNNs and experimentally validated in PlasmoniAC prototypes, revealing significant accuracy and or bandwidth relaxation benefits. Finally, PlasmoniAC successfully merged its innovative DL framework with an established photonic circuitry simulation suite (VPI), migrating its models and algorithms in a powerful VPI-PyTorch co-simulation suite.
Prototyping and application benchmarking. In view of both safeguarding the deployment of PlasmoniAC’s photonic architectures in tangible integrated prototypes and benchmarking its architectures in different plasmo-photonic integration platforms, PlasmoniAC laid out a four-folded development roadmap that encompassed the development of four generations of photonic accelerator prototypes, that concluded to a 4x4 Xbar prototype using SiGe EAM for up to 50 Gbaud operation and a POH-based design that will include Phase Change Materials. Finally, PlasmoniAC assessed the performance of its fabricated prototypes through the experimental deployment of a wide range of DL datasets for: (i) image recognition e.g. MNIST, CIFAR-10, (ii) application specific NN-classifiers for cybersecurity network traffic monitoring i.e. DDOS reconnaissance attack identification and optical communication i.e. NN-assisted channel equalization.
Activities related to the development and integration of the BTO modulators and graphene PDs led to the founding of two start-up companies by IBM and AMO respectively. In addition, AUTH’s and MLNX (NVIDIA)’s pioneering work in the fields of photonic accelerators and network cybersecurity led to 4 US patents.
The multi-disciplinary research of PlasmoniAC has led to over 20 journal articles and appearance in 50 conferences proceedings including 20 invited talks. Finally, PlasmoniAC successfully co-organized two workshops in “Neuromorphic Photonics”, that attracted worldwide attention from both academia and industry while also promoting collaboration between relevant EU Horizon programs.
PlasmoniAC’s cross-cutting workplan, extending from material technology to photonic accelerator architectures and related applications, enabled beyond the state-of-the-art advancements in multiple fronts. Specifically, PlasmoniAC’s thorough investigation of BTO material properties and its deployment over a low-loss SiN photonic substrate paved the way towards >100 Gbaud optical modulator and extended the portfolio of its spin-off consortium member Lumiphase. On the photonic accelerator front, PlasmoniAC demarcated from the previously prominent unitary MZI-mesh based architectures, enabling for the first-time bijective mapping of the weight matrix in a coherent architecture and leading to 3 related submitted patents. The experimental implementation of this architectural vision during PlasmoniAC, allowed it to reach performance metrics close or even higher to the projects target, i.e. 86 fJ/MAC and 1.33 TMAC/sec/mm2, significantly outperforming electronic counterparts in energy efficiency metrics. Finally, on the network security front PlasmoniAC introduced a radical architectural approach that targeted both a novel framework to identify incoming network cybersecurity threats and a concept of a next generation photonic converged accelerator for smart Network Interface cards (NICs). This approach led to the submission of a new patent for Distributed Denial of Service (DDoS) detection and the first demonstration of DDoS reconnaissance attack identification at 50 Gbaud.