Agile, eXtensible, fast I/O Module for the cyber-physical era

Projektinformationen

AXIOM

ID Finanzhilfevereinbarung: 645496

DOI

10.3030/645496

Projekt abgeschlossen

EK-Unterschriftsdatum 1 Dezember 2014

Startdatum 1 Februar 2015

Enddatum 31 Januar 2018

Finanziert unter

• INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT)

Gesamtkosten

€ 3 945 937,50

EU-Beitrag

€ 3 945 937,50

Koordiniert durch

UNIVERSITA DEGLI STUDI DI SIENA
Italy

CORDIS bietet Links zu öffentlichen Ergebnissen und Veröffentlichungen von HORIZONT-Projekten.

Links zu Ergebnissen und Veröffentlichungen von RP7-Projekten sowie Links zu einigen Typen spezifischer Ergebnisse wie Datensätzen und Software werden dynamisch von OpenAIRE abgerufen.

Leistungen

Documents, reports (9)

Report on AXIOM Events

The consultation and validation activities with the external communities will mainly take place through the foreseen 3 industrial workshops that will be organized by the project (by AXIOM industrial actors).

Evaluation of the compiler and tools infrastructure

After the first prototype AXIOM board will be delivered, the testing will be necessary to verify the initial software toolchain. Final research results will be included in this deliverable.

Design Space Exploration (DSE) on the prototype for the AXIOM

Definition and development of appropriate Design Space Exploration (DSE) tools and methodologies.

Final Report on AXIOM Events

The AXIOM final conference will be organized close to the end of the project ideally as a satellite event at a larger international conference. The conference will target to present and validate AXIOM final outcomes and mostly communicate the anticipated next steps at research and innovation level.

Initial AXIOM Evaluation Platform (AEP) definition and initial tests

Definition of the AXIOM evaluation platform (AEP) appropriate for Cyber-Physical Systems

Technical specifications of AXIOM board

This deliverable is a report outlining the most relevant system architecture details

Programming model extensions

This deliverable include the final API document and the software developed, released as Open-Source Software, and added to the BSC website (pm.bsc.es/mcxx).

Performance and energy evaluation of the AXIOM

Integrate in the evaluation platform the main results from all the all work packages.

Scenarios and requirements and Report

Scenario collection and production in the domain of Smart Home/Living (SHL) and Smart Video-Surveillance (SVS) carried out by Contextual Inquiries methods on the field with end Users and Stakeholders.

Other (4)

Final operating system and documentation

This deliverable will consist in an update of deliverable D5.3 containing also the mechanism for load balancing. An additional document will provide the analysis of the real-time guarantees that the system can meet.

Parallel programming library and documentation

This deliverable will consist in an update of deliverable D5.1 with the addition of the Linux kernel driver for the high-speed interconnect developed in Task 5.1, the Remote Memory Access mechanism developed in Task 5.2 and the library for parallel programming developed in Task 5.3.

AXIOM code generation and instrumentation

Documentation for the prototype compiler and first comparative research results is included in this deliverable.

Report on proof of concepts

Selection, envisioning and refinement of Scenarios to be put in to scene by prototypes of AXIOM architecture in the domain of Smart Living/Home (SLH) and Smart Video-Surveillance (SVS). Porting of the Smart Living/Home Application and Smart Video-Surveillance to the OmpSs Programming Model

Websites, patent fillings, videos etc. (1)

Project web site

The goal of this deliverable is to create a web site for the AXIOM project. The site will contain a public part that will serve as a point of visibility for people outside the consortium to make enquiries about the project and to obtain publicly available documentation. Besides the public part, the web site will have part with controlled access, where only partners in the project will be allowed. This part will contain deliverables and reports that have restricted dissemination level, and drafts of deliverables that are being prepared. It will also provide collaborative tools (e.g., wiki) that can be used by multiple partners for collaborating on reports and deliverables.

Veröffentlichungen

Thesis and dissertations (2)

Efficient network interface design for low cost distributed systems

Autoren: Amourgianos-Lorentzos, Vasileios
Veröffentlicht in: 2017
Herausgeber: Technical University of Crete

Asynchronous runtime for task-based dataflow programming models

Autoren: Bosch Pons, J
Veröffentlicht in: 2017
Herausgeber: Universitat Politecnica de Catalunya

Other (2)

A Survey on Hardware and Software Support for Thread Level Parallelism

Autoren: Mazumdar, Somnath and Giorgi Roberto
Veröffentlicht in: 2016
Herausgeber: ArXiv

Coarse-grain performance estimator for heterogeneous parallel computing architectures like Zynq all-programmable SoC

Autoren: D. Jiménez-González, C. Álvarez, A. Filgueras, X. Martorell, J. Langer, J. Noguera, K. Vissers
Veröffentlicht in: 2015
Herausgeber: arXiv

Peer reviewed articles (7)

Simulating Next-Generation Cyber-Physical Computing Platforms

Autoren: Burgio P.; Alvarez C.; Ayguadé E.; Filgueras A.; Jiménez-González D.; Martorell X.; Navarro N. and Giorgi R.
Veröffentlicht in: Ada User Journal, Ausgabe 36 (4), 2015, ISSN 1381-6551
Herausgeber: Ada Language UK Ltd.

Modeling Multi-board Communication in the AXIOM Cyber-Physical System

Autoren: Giorgi, R; , Mazumdar, S.; Viola, S.; Gai, P.; Garzarella, S.; Morelli, B.; Pnevmatikatos, D.; Theodoropoulos, D.; Álvarez, C.; Ayguadé, E.; Bueno, J.; Filgueras, A.; Jiménez-González, D; Martorell, X.
Veröffentlicht in: Ada User journal, Ausgabe 37 (4), 2016, Seite(n) 228-235, ISSN 1381-6551
Herausgeber: Ada Language UK Ltd.

Transactional Memory on a Dataflow Architecture for Accelerating Haskell

Autoren: Roberto Giorgi
Veröffentlicht in: WSEAS Transactions on Computers, Ausgabe Vol. 14, 2015, Seite(n) 546-558, ISSN 1109-2750
Herausgeber: World Scientific and Engineering Academy and Society

A Data-Flow Soft-Core Processor for Accelerating Scientific Calculation on FPGAs

Autoren: Verdoscia, Lorenzo; Giorgi, Roberto
Veröffentlicht in: Mathematical Problems in Engineering, 2016, Seite(n) 1-21, ISSN 1563-5147
Herausgeber: Hindawi
DOI: 10.1155/2016/3190234

The AXIOM Software Layers

Autoren: Alvarez, Carlos; Ayguade, Eduard; Bosch, Jaume; Bueno, Javier; Cherkashin, Artem; Filgueras, Antonio; Jiminez-Gonzalez, Daniel; Martorell, Xavier; Navarro, Nacho; Vidal, Miquel; Theodoropoulos, Dimitris; Pnevmatikatos, Dionisios; Catani, Davide; Oro, David; Fernandez, Carles; Segura, Carlos; Rodriguez, Javier; Hernando, Javier; Scordino, Claudio; Gai, Paolo; Passera, Pierluigi; Pomella, Aberto; Be
Veröffentlicht in: ELSEVIER Microprocessors and Microsystems, Ausgabe 47 (B), 2016, Seite(n) 262-277, ISSN 0141-9331
Herausgeber: Elsevier BV
DOI: 10.1016/j.micpro.2016.07.002

Making IoT with UDOO

Autoren: Rizzo, Antonio; Burresi, Giovanni; Montefoschi, Francesco; Caporali, Maurizio; Giorgi, Roberto
Veröffentlicht in: Interaction Design and Architecture(s), Ausgabe 1 (30), 2016, Seite(n) 95-112, ISSN 1826-9745
Herausgeber: ?

Simulating next-generation Cyber-physical computing platforms

Autoren: Burgio, Paolo; Alvarez, Carlos; Ayguade, Eduard; Filgueras, Antonio; Jiminez-Gonzalez, Daniel; Martorell, Xavier; Navarro, Nacho; Giorgi, Roberto
Veröffentlicht in: Ada User Journal, Ausgabe 37 (1), 2016, Seite(n) 59-63, ISSN 1381-6551
Herausgeber: Ada Language UK Ltd.

Conference proceedings (1)

Accelerating Haskell on a Dataflow Architecture: a case study including Transactional Memory

Autoren: Roberto Giorgi
Veröffentlicht in: Proc. Int.l Conf. on Computer Engineering and Applications (CEA), 2015, Seite(n) 91–100, ISBN 978-1-61804-276-7
Herausgeber: ?