Memory technologies with multi-scale time constants for neuromorphic architectures

Project Information

MeM-Scales

Grant agreement ID: 871371

DOI

10.3030/871371

Project closed

EC signature date 5 December 2019

Start date 1 January 2020

End date 30 June 2023

Funded under

• INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT)

Total cost

€ 3 950 628,75

EU contribution

€ 3 950 628,75

Coordinated by

COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
France

CORDIS provides links to public deliverables and publications of HORIZON projects.

Links to deliverables and publications from FP7 projects, as well as links to some specific result types such as dataset and software, are dynamically retrieved from OpenAIRE .

Deliverables

Other (1)

Project web-site on line with public and restricted areas and project logo defined

Project website on line with public and restricted areas and project logo defined

Documents, reports (9)

Report on test structures including memory devices with short-to-medium timescales

Report on test structures including memory devices with shorttomedium timescales

Report describing use-cases and benchmarks for non-conventional memory devices

Report describing usecases and benchmarks for nonconventional memory devices

Layout and circuit simulation results of the multi-time scale analog synapse and neuron circuits

Layout and circuit simulation results of the multitime scale analog synapse and neuron circuits

Report on theoretical models benchmarking
Report on CMOS circuit implementation for local synapse array, including how the interfaces to the TFT neuron chip have been properly dealt with

Report on CMOS circuit implementation for local synapse array including how theinterfaces to the TFT neuron chip have been properly dealt with

Report on options for the computational extension of physically obtained timescales
Summary report on lessons learnt about hardware- and application-centered timescale management

Summary report on lessons learnt about hardware and applicationcentered timescale management

Description and simulation results of the asynchronous circuits used for multi-core routing

Description and simulation results of the asynchronous circuits used for multicore routing

Report comprising (i) a critical survey of existing proposed models of unconventional computing, and (ii) a novel proposal for (components of) a model of computing in indeterminate hardware which resolves (some of) the defects found in existing approaches

Report comprising i a critical survey of existing proposed models of unconventionalcomputing and ii a novel proposal for components of a model of computing in indeterminate hardware which resolves some of the defects found in existing approaches

Demonstrators, pilots, prototypes (1)

Chip software interface for controlling biases, sending input spiketrains and receiving output spike trains

Chip software interface for controlling biases sending input spiketrains and receiving output spike trains

Publications

Conference proceedings (7)

Implementation of binary stochastic STDP learning using chalcogenide-based memristive devices

Author(s): C. Mohan, L. A. Camuñas-Mesa, J. M. de la Rosa, T. Serrano-Gotarredona, B. Linares-Barranco
Published in: Proceedings of the 2021 IEEE Int. Symp. on circ. and Syst., Issue annual, 2021
Publisher: IEEE

Empirical study on the efficiency of Spiking Neural Networks with axonal delays, and algorithm-hardware benchmarking

Author(s): Alberto Patiño-Saucedo, Amirreza Yousefzadeh, Guangzhi Tang, Federico Corradi, Bernabé Linares-Barranco, Manolis Sifalakis
Published in: Proceedings of the 2023 IEEE Symposium on Circuits and Systems, Issue annual, 2023
Publisher: IEEE
DOI: 10.1109/iscas46773.2023.10181778

Dendritic Computation through Exploiting Resistive Memory as both Delays and Weights

Author(s): Melika Payvand, Simone D'Agostino, Filippo Moro, Yigit Demirag, Giacomo Indiveri, Elisa Vianello
Published in: ACM ICONS 2023, 2023, ISBN 978-1-4503-9789-6
Publisher: ACM

Experimental Body-Input Three-Stage DC Offset Calibration Scheme for Memristive Crossbar

Author(s): Charanraj Mohan, L. A. Camunas-Mesa, Elisa Vianello, Carlo Reita, Jose M. de la Rosa, Teresa Serrano-Gotarredona, Bernabe Linares-Barranco
Published in: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Issue annual, 2020, Page(s) 1-5, ISBN 978-1-7281-3320-1
Publisher: IEEE
DOI: 10.1109/iscas45731.2020.9180811

Synaptic metaplasticity with multi-level memristive devices

Author(s): Simone D'Agostino, Filippo Moro, Tifenn Hirtzlin, Julien Arcamone, Niccolò Castellani, Damien Querlioz, Melika Payvand, Elisa Vianello
Published in: 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2023, ISBN 978-1-7281-9201-7
Publisher: IEEE
DOI: 10.1109/aicas57966.2023.10168563

PCM-Trace: Scalable Synaptic Eligibility Traces with Resistivity Drift of Phase-Change Materials

Author(s): Yigit Demirag; Filippo Moro; Thomas Dalgaty; Gabriele Navarro; Charlotte Frenkel; Giacomo Indiveri; Elisa Vianello; Melika Payvand
Published in: ISCAS, Issue 2, 2021, ISBN 978-1-7281-9201-7
Publisher: IEEE
DOI: 10.1109/iscas51556.2021.9401446

Hardware calibrated learning to compensate heterogeneity in analog RRAM-based Spiking Neural Networks

Author(s): Filippo Moro, E. Esmanhotto, T. Hirtzlin, N. Castellani, A. Trabelsi, T. Dalgaty, G. Molas, F. Andrieu, S. Brivio, S. Spiga, G. Indiveri, M. Payvand, and E. Vianello
Published in: Proceedings of the 2022 IEEE Int. Symp. on circ. and Syst., 2022, ISBN 978-1-7281-3320-1
Publisher: IEEE
DOI: 10.1109/iscas48785.2022.9937820

Peer reviewed articles (10)

Toward a formal theory for computing machines made out of whatever physics offers

Author(s): Jaeger, H., Noheda, B. & van der Wiel, W.G.
Published in: Nature Communications, Issue 14, 2023, Page(s) 4911, ISSN 2041-1723
Publisher: Nature Publishing Group
DOI: 10.1038/s41467-023-40533-1

Toward a generalized theory comprising digital, neuromorphic, and unconventional computing

Author(s): Herbert Jaeger
Published in: Neuromorphic computing and engineering, 1:012002. IOP PUBLISHING LTD, Issue 1, 2021, ISSN 2634-4386
Publisher: IOP PUBLISHING LTD
DOI: 10.1088/2634-4386/abf151

2022 roadmap on neuromorphic computing and engineering

Author(s): Dennis V Christensen; Regina Dittmann; Bernabe Linares-Barranco; Abu Sebastian; Manuel Le Gallo; Andrea Redaelli; Stefan Slesazeck; Thomas Mikolajick; Sabina Spiga; Stephan Menzel; Ilia Valov; Gianluca Milano; Carlo Ricciardi; Shi-Jun Liang; Feng Miao; Mario Lanza; Tyler J Quill; Scott T Keene; Alberto Salleo; Julie Grollier; Danijela Marković; Alice Mizrahi; Peng Yao; J Joshua Yang; Giacomo Indi
Published in: Furber , S & et , A 2022 , ' 2022 roadmap on neuromorphic computing and engineering ' , Neuromorphic Computing and Engineering , vol. 2 , no. 2 . https://doi.org/10.1088/2634-4386/ac4a83, Issue 16, 2022, ISSN 1742-6588
Publisher: Institute of Physics
DOI: 10.17863/cam.85857

Ultra-Low-Power FDSOI Neural Circuits for Extreme-Edge Neuromorphic Intelligence

Author(s): Arianna Rubino; Can Livanelioglu; Ning Qiao; Melika Payvand; Giacomo Indiveri
Published in: IEEE Transactions on Circuits and Systems I: Regular Papers, 68 (1), Issue 5, 2020, ISSN 1549-8328
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tcsi.2020.3035575

a roadmap

Author(s): Abad, B; Alberi, K; Ayers, KE; Badhulika, S; Ban, C; Béa, H; Béron, F; Cairney, J; Chang, JP; Charles, C; Creatore, M; Dong, H; Du, J; Egan, R; Everschor-Sitte, K; Foley, C; Fontcuberta I Morral, A; Jung, MH; Kim, H; Kurtz, S; Lee, J; Leitao, DC; Lemmer, K; Marschilok, AC; Mitu, B; Newman, BK; Owens, R; Pappa, AM; Park, Y; Peckham, M; Rossi, LM; Shim, SH; Siddiqui, SA; Son, JW; Spiga, S; Tsikata
Published in: VOLUME=56;ISSUE=7;ISSN=0022-3727;TITLE=Journal of Physics D: Applied Physics, Issue 15, 2023, ISSN 1742-6588
Publisher: Institute of Physics
DOI: 10.1088/1361-6463/ac82f9

Self-organization of an inhomogeneous memristive hardware for sequence learning

Author(s): Melika Payvand, Filippo Moro, Kumiko Nomura, Thomas Dalgaty, Elisa Vianello, Yoshifumi Nishi & Giacomo Indiveri
Published in: Nature Communications, 2022, ISSN 2041-1723
Publisher: Nature Publishing Group
DOI: 10.1038/s41467-022-33476-6

In situ learning using intrinsic memristor variability via Markov chain Monte Carlo sampling

Author(s): Thomas Dalgaty, Niccolo Castellani, Clément Turck, Kamel-Eddine Harabi, Damien Querlioz, Elisa Vianello
Published in: Nature Electronics, Issue 4/2, 2021, Page(s) 151-161, ISSN 2520-1131
Publisher: Nature
DOI: 10.1038/s41928-020-00523-3

Neuromorphic object localization using resistive memories and ultrasonic transducers

Author(s): Filippo Moro, Emmanuel Hardy, Bruno Fain, Thomas Dalgaty, Paul Clémençon, Alessio De Prà, Eduardo Esmanhotto, Niccolò Castellani, François Blard, François Gardien, Thomas Mesquida, François Rummens, David Esseni, Jérôme Casas, Giacomo Indiveri, Melika Payvand & Elisa Vianello
Published in: Nat Commun, 2022, ISSN 2041-1723
Publisher: Nature Publishing Group
DOI: 10.1038/s41467-022-31157-y

Neuromorphic Low-power Inference on Memristive Crossbars with On-chip Offset Calibration

Author(s): Charanraj Mohan, L.A. Camunas-Mesa, Jose M. De La Rosa, Elisa Vianello, Teresa Serrano-Gotarredona, Bernabe Linares-Barranco
Published in: IEEE Access, Issue monthly, 2020, Page(s) 1-1, ISSN 2169-3536
Publisher: Institute of Electrical and Electronics Engineers Inc.
DOI: 10.1109/access.2021.3063437

Non-linear Memristive Synaptic Dynamics for Efficient Unsupervised Learning in Spiking Neural Networks

Author(s): Stefano Brivio, Denys R. B. Ly, Elisa Vianello, Sabina Spiga
Published in: Frontiers in Neuroscience, Issue 15, 2021, Page(s) Article 580909, ISSN 1662-453X
Publisher: Frontiers
DOI: 10.3389/fnins.2021.580909