Cryogenic 3D Nanoelectronics

Información del proyecto

SEQUENCE

Identificador del acuerdo de subvención: 871764

DOI

10.3030/871764

Proyecto cerrado

Fecha de la firma de la CE 5 Diciembre 2019

Fecha de inicio 1 Enero 2020

Fecha de finalización 31 Julio 2023

Financiado con arreglo a

• INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT)

Coste total

€ 4 466 278,75

Aportación de la UE

€ 4 466 277,00

Coordinado por

LUNDS UNIVERSITET
Sweden

CORDIS proporciona enlaces a los documentos públicos y las publicaciones de los proyectos de los programas marco HORIZONTE.

Los enlaces a los documentos y las publicaciones de los proyectos del Séptimo Programa Marco, así como los enlaces a algunos tipos de resultados específicos, como conjuntos de datos y «software», se obtienen dinámicamente de OpenAIRE .

Resultado final

Documents, reports (16)

Final benchmarking towards evolving wideband communication and sensing including identification of limiting factors
Initial benchmarking towards evolving wideband communication and sensing
Final report on electrical parameter, interface dielectric trap and RF (S parameter and NF) characterization of devices operated at cryogenic condition

Final report on electrical parameter interface dielectric trap and RF S parameter and NF characterization of devices operated at cryogenic condition

Report on first version of device compact models for LF and RF circuit simulation
First report on interface dielectric trap and RF (S parameter and NF) characterization of devices operated at cryogenic condition
Web site launch
Report on extremely low temperature (20mK-4K) device characterization

Report on extremely low temperature 20mK4K device characterization

Road map for integrated and improved quantum computer electronics
Report on device compact modelling for LF and RF circuit simulation
Report on self heating device characterization by thermal and electrical techniques
Review of key building blocks for cryogenic logic and space, 40-70 K, as well as wideband communication, RT
First report on electrical characterization and parameter extraction of devices operated at cryogenic condition
External Communication Plan
Dissemination Plan
Final Dissemination Plan
Initial report on circuit design with layouts and simulated performance

Publicaciones

Peer reviewed articles (17)

On the diffusion current in a MOSFET operated down to deep cryogenic temperatures

Autores: G. Ghibaudo, M. Aouad, M. Casse, T. Poiroux, C. Theodorou
Publicado en: Solid-State Electronics, Edición 176, 2021, Página(s) 107949, ISSN 0038-1101
Editor: Pergamon Press Ltd.
DOI: 10.1016/j.sse.2020.107949

Performance and Low-Frequency Noise of 22-nm FDSOI Down to 4.2 K for Cryogenic Applications

Autores: Bruna Cardoso Paz, Mikael Casse, Christoforos Theodorou, Gerard Ghibaudo, Thorsten Kammler, Luca Pirro, Maud Vinet, Silvano de Franceschi, Tristan Meunier, Fred Gaillard
Publicado en: IEEE Transactions on Electron Devices, Edición 67/11, 2020, Página(s) 4563-4567, ISSN 0018-9383
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/ted.2020.3021999

First Demonstration of Distributed Amplifier MMICs With More Than 300-GHz Bandwidth

Autores: Fabian Thome, Arnulf Leuther
Publicado en: IEEE Journal of Solid-State Circuits, 2021, Página(s) 1-1, ISSN 0018-9200
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/jssc.2021.3052952

Optimization of Near‐Surface Quantum Well Processing

Autores: Patrik Olausson, Lasse Södergren, Mattias Borg, Erik Lind
Publicado en: physica status solidi (a), Edición 218/7, 2021, Página(s) 2000720, ISSN 1862-6300
Editor: Wiley - V C H Verlag GmbbH & Co.
DOI: 10.1002/pssa.202000720

Tuning of Source Material for InAs/InGaAsSb/GaSb Application-Specific Vertical Nanowire Tunnel FETs

Autores: Abinaya Krishnaraja, Johannes Svensson, Elvedin Memisevic, Zhongyunshen Zhu, Axel R. Persson, Erik Lind, Lars Reine Wallenberg, Lars-Erik Wernersson
Publicado en: ACS Applied Electronic Materials, Edición 2/9, 2020, Página(s) 2882-2887, ISSN 2637-6113
Editor: ACS
DOI: 10.1021/acsaelm.0c00521

Evidence of 2D intersubband scattering in thin film fully depleted silicon-on-insulator transistors operating at 4.2 K

Autores: Mikaël Cassé, Bruna Cardoso Paz, Gérard Ghibaudo, Thierry Poiroux, Emmanuel Vincent, Philippe Galy, André Juge, Fred Gaillard, Silvano de Franceschi, Tristan Meunier, Maud Vinet
Publicado en: Applied Physics Letters, Edición 116/24, 2020, Página(s) 243502, ISSN 0003-6951
Editor: American Institute of Physics
DOI: 10.1063/5.0007100

Simulation of low-noise amplifier with quantized ballistic nanowire channel

Autores: Christian Marty, Clarissa Convertino, Cezar Zota
Publicado en: Semiconductor Science and Technology, Edición 35/11, 2020, Página(s) 115027, ISSN 0268-1242
Editor: Institute of Physics Publishing
DOI: 10.1088/1361-6641/abb841

The Role of Oxide Traps Aligned With the Semiconductor Energy Gap in MOS Systems

Autores: Enrico Caruso, Jun Lin, Scott Monaghan, Karim Cherkaoui, Farzan Gity, Pierpaolo Palestri, David Esseni, Luca Selmi, Paul K. Hurley
Publicado en: IEEE Transactions on Electron Devices, Edición 67/10, 2020, Página(s) 4372-4378, ISSN 0018-9383
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/ted.2020.3018095

A hybrid III–V tunnel FET and MOSFET technology platform integrated on silicon

Autores: Clarissa Convertino, Cezar B. Zota, Heinz Schmid, Daniele Caimi, Lukas Czornomaz, Adrian M. Ionescu, Kirsten E. Moselund
Publicado en: Nature Electronics, Edición 4/2, 2021, Página(s) 162-170, ISSN 2520-1131
Editor: Nature
DOI: 10.1038/s41928-020-00531-3

InGaAs MOSHEMT W -Band LNAs on Silicon and Gallium Arsenide Substrates

Autores: Fabian Thome, Felix Heinz, Arnulf Leuther
Publicado en: IEEE Microwave and Wireless Components Letters, Edición 30/11, 2020, Página(s) 1089-1092, ISSN 1531-1309
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/lmwc.2020.3025674

III-V-on-Si transistor technologies: Performance boosters and integration

Autores: D. Caimi, H. Schmid, T. Morf, P. Mueller, M. Sousa, K.E. Moselund, C.B. Zota
Publicado en: Solid-State Electronics, Edición 185, 2021, Página(s) 108077, ISSN 0038-1101
Editor: Pergamon Press Ltd.
DOI: 10.1016/j.sse.2021.108077

Scaled III-V-on-Si Transistors for Low-Power Logic and Memory Applications

Autores: Daniele Caimi, Marilyne Sousa, Siegfried Karg and Cezar B. Zota
Publicado en: Japanese Journal of Applied Physics, Edición 60/SB, 2021, Página(s) SB0801, ISSN 0021-4922
Editor: IOP Science
DOI: 10.35848/1347-4065/abd707

Generalized Boltzmann relations in semiconductors including band tails

Autores: Arnout Beckers, Dominique Beckers, Farzan Jazaeri, Bertrand Parvais, Christian Enz
Publicado en: Journal of Applied Physics, Edición 129/4, 2021, Página(s) 045701, ISSN 0021-8979
Editor: American Institute of Physics
DOI: 10.1063/5.0037432

Mobility of near surface MOVPE grown InGaAs/InP quantum wells

Autores: Lasse Södergren, Navya Sri Garigapati, Mattias Borg, Erik Lind
Publicado en: Applied Physics Letters, Edición 117/1, 2020, Página(s) 013102, ISSN 0003-6951
Editor: American Institute of Physics
DOI: 10.1063/5.0006530

Heterogeneous Integration of III-V Materials by Direct Wafer Bonding for High-Performance Electronics and Optoelectronics

Autores: Daniele Caimi, Preksha Tiwari, Marilyne Sousa, Kirsten E. Moselund, Cezar B. Zota
Publicado en: IEEE Transactions on Electron Devices, 2021, Página(s) 1-8, ISSN 0018-9383
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/ted.2021.3067273

Millimeter-Wave Vertical III-V Nanowire MOSFET Device-to-Circuit Co-Design

Autores: Stefan Andric, Lars Ohlsson Fhager, Lars-Erik Wernersson
Publicado en: IEEE Transactions on Nanotechnology, Edición 20, 2021, Página(s) 434-440, ISSN 1536-125X
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tnano.2021.3080621

Cryogenic Operation of Thin-Film FDSOI nMOS Transistors: The Effect of Back Bias on Drain Current and Transconductance

Autores: M. Casse, B. Cardoso Paz, G. Ghibaudo, T. Poiroux, S. Barraud, M. Vinet, S. de Franceschi, T. Meunier, F. Gaillard
Publicado en: IEEE Transactions on Electron Devices, Edición 67/11, 2020, Página(s) 4636-4640, ISSN 0018-9383
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/ted.2020.3022607

Conference proceedings (6)

Design of III-V Vertical Nanowire MOSFETs for Near-Unilateral Millimeter-Wave Operation

Autores: Stefan Andrić, Lars Ohlsson-Fhager, Lars-Erik Wernersson
Publicado en: Edición 10-15 Jan. 2021, 2020
Editor: IEEE

Poisson-Schrödinger simulation of inversion charge in FDSOI MOSFET down to 0K - Towards compact modeling for cryo CMOS application

Autores: M. Aouad, S. Martinie, F. Triozon, T. Poiroux, M. Vinet, G. Ghibaudo
Publicado en: 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2020, Página(s) 1-4, ISBN 978-1-7281-8765-5
Editor: IEEE
DOI: 10.1109/eurosoi-ulis49407.2020.9365297

Vertical InAs/InGaAsSb/GaSb Nanowire Tunnel FETs on Si with Drain Field-Plate and EOT = 1 nm Achieving S min = 32 mV/dec and g m /I D = 100 V -1

Autores: Abinaya Krishnaraja, Johannes Svensson, Lars-Erik Wernersson
Publicado en: 2020 IEEE Silicon Nanoelectronics Workshop (SNW), 2020, Página(s) 17-18, ISBN 978-1-7281-9735-7
Editor: IEEE
DOI: 10.1109/snw50361.2020.9131656

III-V Nanowire MOSFETs: RF-Properties and Applications

Autores: Lars-Erik Wernersson
Publicado en: 2020 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2020, Página(s) 1-4, ISBN 978-1-7281-9749-4
Editor: IEEE
DOI: 10.1109/bcicts48439.2020.9392932

Cryo-CMOS Compact Modeling

Autores: Christian Enz, Arnout Beckers, Farzan Jazaeri
Publicado en: 2020 IEEE International Electron Devices Meeting (IEDM), 2020, Página(s) 25.3.1-25.3.4, ISBN 978-1-7281-8888-1
Editor: IEEE
DOI: 10.1109/iedm13553.2020.9371894

Ultra-Low Power Scaled III-V-on-Si 1T-DRAMs With Quantum Well Heterostructures

Autores: C. Convertino, L. Vergano, L. Czornomaz, C. B. Zota, S. Karg
Publicado en: 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2020, Página(s) 1-4, ISBN 978-1-7281-8765-5
Editor: IEEE
DOI: 10.1109/eurosoi-ulis49407.2020.9365288

Book chapters (1)

Low Temperature Characterization and Modeling of FDSOI Transistors for Cryo CMOS Applications

Autores: Mikaël Cassé, Gérard Ghibaudo
Publicado en: Low-Temperature Technologies [Working Title], 2021
Editor: IntechOpen
DOI: 10.5772/intechopen.98403