Towards EXtreme scale Technologies and Accelerators for euROhpc hw/Sw Supercomputing Applications for exascale

Información del proyecto

TEXTAROSSA

Identificador del acuerdo de subvención: 956831

DOI

10.3030/956831

Proyecto cerrado

Fecha de la firma de la CE 31 Marzo 2021

Fecha de inicio 1 Abril 2021

Fecha de finalización 31 Marzo 2024

Financiado con arreglo a

• INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT)

Coste total

€ 6 012 708,75

Aportación de la UE

€ 2 051 376,42

Coordinado por

AGENZIA NAZIONALE PER LE NUOVE TECNOLOGIE, L'ENERGIA E LO SVILUPPO ECONOMICO SOSTENIBILE
Italy

CORDIS proporciona enlaces a los documentos públicos y las publicaciones de los proyectos de los programas marco HORIZONTE.

Los enlaces a los documentos y las publicaciones de los proyectos del Séptimo Programa Marco, así como los enlaces a algunos tipos de resultados específicos, como conjuntos de datos y «software», se obtienen dinámicamente de OpenAIRE .

Resultado final

Demonstrators, pilots, prototypes (10)

eXtreme Secure Crypto IP, part 2

Technical report and database of the secure IP supporting lattice cryptography (synthesizable in the FPGA-based IDV of WP5). Part 2.

IP for low-latency inter-node communication links, part 2

Technical report and database (synthesizable in the FPGA-based IDV of WP5) of the IP for low-latency inter-node communication links. Part 2.

IP for fast task scheduling, part 2

Technical report and database (synthesizable in the FPGA based IDV of WP5) of the IP for fast task scheduling. Part 2.

IP with data compression, part 1

Technical report and database of the data compression IP (synthesizable in the FPGA-based IDV of WP5). Part 1.

AI Accelerator with mixed-precision including Posit, part 2

Technical report and database of the data compression IP (synthesizable in the FPGA-based IDV of WP5). Part 2.

IP with data compression, part 2

Technical report and database of the data compression IP (synthesizable in the FPGA-based IDV of WP5). Part 2.

AI Accelerator with mixed-precision including Posit, part 1

Technical report and database of the AI accelerator IP (synthesizable in the FPGA-based IDV of WP5). Part 1.

IP for low-latency inter-node communication links, part 1

Technical report and database (synthesizable in the FPGA-based IDV of WP5) of the IP for low-latency inter-node communication links. Part 1.

eXtreme Secure Crypto IP, part 1

Technical report and database of the secure IP supporting lattice cryptography (synthesizable in the FPGA-based IDV of WP5). Part 1

IP for fast task scheduling, part 1

Technical report and database (synthesizable in the FPGA based IDV of WP5) of the IP for fast task scheduling. Part 1.

Documents, reports (18)

Communication and Dissemination Report 2

The final report provides a summary of the dissemination actions undertaken during the project, as well as an overview of the plans of the partners to further disseminate the generated knowledge beyond the lifetime of the project.

Benchmarking design and planning

Benchmark results carried out on the available HPC platforms.

Project Flyer & Dissemination Materials

The deliverable includes a set of communication and dissemination materials targeting a variety of stakeholders

Update of the collaboration plan with definition of common objectives and activities including milestones

Update on the report on the identification of common objectives and the definition and implementation of a collaboration plan, including the definition of the related project-specific milestones.

Evaluation plan

This deliverable provides initial results of T6.4 to orchestrate evaluation of TEXTAROSSA solutions.

Final report of the collaboration plan with definition of common objectives and activities including milestones

Final report on the identification of common objectives and the definition and implementation of a collaboration plan, including the definition of the related project-specific milestones.

Communication, Dissemination and Awareness Raising Strategy

This deliverable deals with the overall communication dissemination and raising awareness strategy of the project including target audience means to reach the audience and procedures to follow for this scope

Project management and handbook

The deliverable includes management processes and a complete handbook to share information set up internal processes and align activities

Collaboration plan with definition of common objectives and activities including milestones

The final report provides a summary of the dissemination actions undertaken during the project as well as an overview of the plans of the partners to further disseminate the generated knowledge beyond the lifetime of the project

Requirements & Specifications

Definition of the specific technologies that will be used to exploit the applications.

Proof of Concept Design

Design of HW and SW prototypes able to achieve the KPIs of the objectives.

Communication and Dissemination Report 1

This deliverable reports on the dissemination actions undertaken during the first reporting period, as well as an overview of the plans of the partners to further disseminate the generated knowledge during the second period. It also includes the plan for the book. This report covers the training and networking too.

Consolidated specs of accelerators IPs

Technical report with consolidated specifications and requirements for the IPs that will be developed in WP2.

Gap analysis

State-of-art of all technologies involved in the proposal

External Advisory Board reports

Description of the advisory board and its actions to support technological TEXTAROSSA activities. It includes a “Lesson learnt'' section.

Initial application benchmarks and results

This deliverable provides intermediate results of T6.1-T6.3 tasks to present the initial benchmarks of applications and kernels i) adapted to heterogeneous architectures, ii) which exploit mixed-precision and iii) which benefit from dynamic runtime.

Data management plan

A data management plan will be discussed with all partners and will be implemented in agreement with Open Science directives

Final assessment and guidelines

This deliverable summarizes adaptation of TEXTAROSSA features (T6.1-T6.3), provides guidelines, recommendations and final evaluation of the project (T6.4).

Other (7)

HLS flow

This deliverable consists on the final version of Vitis HLS flow, supporting the new HW defined in the project (selected FPGA family and board, mixed precision, inter-FPGA communication) at all the levels (emulation, simulation synthesis). The Vitis HLS flow version will be compliant with the interfaces defined toward the run-time.

Project Website & Social Media

The deliverable includes website and social media (Facebook, Twitter) accounts managed by the project consortium.

Inter-FPGA Communication SW Stack

This deliverable consists in the SW stack (kernel device driver and user-space library) needed to configure, control and monitor the Communication IP and to support its integration in the Vitis HLSflow.

Framework for efficient CNNs inference on a TEXTAROSSA node

This deliverable from T4.6 consists in the solutions to reduce communications for CNNs at the server level and a set of efficient CNN kernels for heterogeneous architectures enhanced with FPGA.

Efficient Memory Management strategies for CNNs at node level

This deliverable consists of the SW layer implemented into the runtime system to manage CNN applications. This is an intermediate result of Task 4.6.

Mixed precision tool suite

This deliverable from T4.3 consists of compilers, interfaces, libraries and tools needed to support mixed-precision computing in the node.

Task-based runtime systems

This deliverable consists in OmpSs and StarPU adapted to TEXTAROSSA node and that support the features implemented in this WP. This is the outcome of tasks 4.2, 4.4 and 4.5.

Open Research Data Pilot (1)

Risk management plan

The deliverable describes what actions will be undertaken to reduce project risks at all levels.

Publicaciones

Conference proceedings (29)

Experiments on Speeding Up the Recursive Fast Fourier Transform by using AVX-512 SIMD instructions

Autores: Giacomo Sansone, Marco Cococcioni
Publicado en: International Conference on Applications in Electronics Pervading Industry, Environment and Society (ApplePies), 2022
Editor: Springer Nature
DOI: 10.5281/zenodo.7134224

Using High-Level Synthesis to program parallel structures: the FPGA Image Processing Library

Autores: Palazzari P., Iannone F.
Publicado en: Special Edición of the International Journal of Parallel Programming, 2024
Editor: Springer

FPGA implementation of BIKE for quantum-resistant TLS

Autores: Galimberti, Andrea; Galli, Davide; Montanaro, Gabriele; Fornaciari, William; Zoni, Davide
Publicado en: 2022 25th Euromicro Conference on Digital System Design (DSD), Edición 1, 2022, ISBN 978-1-6654-7404-7
Editor: IEEE
DOI: 10.1109/dsd57027.2022.00078

Ahead-Of-Real-Time (ART): A Methodology for Static Reduction of Worst-Case Execution Time

Autores: Cattaneo, Daniele ; Magnani, Gabriele ; Cherubin, Stefano ; Agosta, Giovanni
Publicado en: Third Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2022), 2022, ISBN 978-3-95977-221-1
Editor: Schloss Dagstuhl -- Leibniz-Zentrum fur Informatik
DOI: 10.4230/oasics.ng-res.2022.4

Hardware and Software Support for Mixed Precision Computing: a Roadmap for Embedded and HPC Systems

Autores: Fornaciari W.; Agosta G.; Cattaneo D.; Denisov L.; Galimberti A.; Magnani G.; Zoni D.
Publicado en: 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), Edición 13, 2023, ISBN 979-8-3503-9624-9
Editor: IEEE
DOI: 10.23919/date56975.2023.10137092

The Italian research on HPC key technologies across EuroHPC

Autores: Aldinucci M.; Agosta G.; Andreini A.; Ardagna C. A.; Bartolini A.; Cilardo A.; Cosenza B.; Danelutto M.; Esposito R.; Fornaciari W.; Giorgi R.; Lengani D.; Montella R.; Olivieri M.; Saponara S.; Simoni D.; Torquati M.
Publicado en: Proceedings of the 18th ACM International Conference on Computing Frontiers, Edición 17, 2021
Editor: ACM
DOI: 10.1145/3457388.3458508

FastFlow targeting FPGAs

Autores: Marco Danelutto; Gabriele Mencagli; Alberto Ottimo; Francesco Iannone; Paolo Palazzari
Publicado en: 2023 31st Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), 2023, Página(s) 104-108
Editor: IEEE press
DOI: 10.1109/pdp59025.2023.00023

TEXTAROSSA: Towards EXtreme scale Technologies and Accelerators for euROhpc hw/Sw Supercomputing Applications for exascale

Autores: Giovanni Agosta; Daniele Cattaneo; William Fornaciari; Andrea Galimberti; Giuseppe Massari; Federico Reghenzani; Federico Terraneo; Davide Zoni; Carlo Brandolese; Massimo Celino; F. Iannone; Paolo Palazzari; Giuseppe Zummo; Massimo Bernaschi; Pasqua D'Ambra; Sergio Saponara; Marco Danelutto; Massimo Torquati; Marco Aldinucci; Yasir Arfat; Barbara Cantalupo; Iacopo Colonnelli; Roberto Esposito; Alb
Publicado en: 2021 24th Euromicro Conference on Digital System Design (DSD), 2021
Editor: IEEE
DOI: 10.1109/dsd53832.2021.00051

On the use of hardware accelerators in QC-MDPC code-based cryptography

Autores: Galimberti, Andrea; Galli, Davide; Montanaro, Gabriele; Fornaciari, William; Zoni, Davide
Publicado en: Proceedings of the 19th ACM International Conference on Computing Frontiers, Edición 5, 2022, Página(s) 193-194
Editor: acm
DOI: 10.1145/3528416.3530243

Mixed Precision in Heterogeneous Parallel Computing Platforms via Delayed Code Analysis

Autores: Daniele Cattaneo, Alberto Maggioli, Gabriele Magnani, Lev Denisov, Shufan Yang, Giovanni Agosta, Stefano Cherubin
Publicado en: Embedded Computer Systems: Architectures, Modeling, and Simulation: 23rd International Conference, SAMOS 2023, Edición 1, 2023, Página(s) 469–477, ISBN 978-3-031-46076-0
Editor: Springer
DOI: 10.1007/978-3-031-46077-7_33

Experimental Results of Vectorized Posit-Based DNNs on a Real ARM SVE High Performance Computing Machine

Autores: Marco Cococcioni; Federico Rossi; Emanuele Ruffaldi; Sergio Saponara
Publicado en: Lecture Notes in Electrical Engineering, 2022, ISBN 978-3-030-95497-0
Editor: Springer
DOI: 10.5281/zenodo.7128765

Data Distribution Schemes for Dense Linear Algebra Factorizations on Any Number of Nodes

Autores: Beaumont, Olivier; Collin, Jean-Alexandre; Eyraud-Dubois, Lionel; Vérité, Mathieu
Publicado en: Proceedings of the 37th IEEE International Parallel & Distributed Processing Symposium, Edición 6, 2023, ISBN 979-8-3503-3766-2
Editor: IEEE
DOI: 10.1109/ipdps54959.2023.00047

Task scheduling sensitivity to L1 cache settings on an area-constrained 32-core RISC-V processor

Autores: Morais, Lucas; Jiménez-González, Daniel; Álvarez, Carlos
Publicado en: 9th BSC Doctoral Symposium, 2022
Editor: BSC

Dynamic Tasks Scheduling with Multiple Priorities on Heterogeneous Computing Systems

Autores: Hayfa Tayeb, Bérenger Bramas, Mathieu Faverge, Abdou Guermouche
Publicado en: IEEE Heterogeneity in Computing Workshop (HCW’24), IPDPS 2024, 2024
Editor: IEEE

Hardware-Software Co-Design of BIKE with HLS-Generated Accelerators

Autores: Montanaro G.; Galimberti A.; Colizzi E.; Zoni D.
Publicado en: IEEE International Conference on Electronics, Circuits and Systems (ICECS), Edición 4, 2022, ISBN 978-1-6654-8823-5
Editor: IEEE
DOI: 10.1109/icecs202256217.2022.9970992

An Evaluation of the State-of-the-Art Software and Hardware Implementations of BIKE

Autores: Andrea Galimberti; Gabriele Montanaro; William Fornaciari; Davide Zoni
Publicado en: 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023), Edición 6, 2023
Editor: oasic
DOI: 10.4230/oasics.parma-ditam.2023.4

Robust Learning via Golden Symmetric Loss of (un)Trusted Labels

Autores: Amirmasoud Ghiassi, Robert Birke and Lydia Y. Chen
Publicado en: Cover Image Proceedings of the 2023 SIAM International Conference on Data Mining (SDM), Edición 2023, 2023, ISBN 978-1-61197-765-3
Editor: SIAM
DOI: 10.1137/1.9781611977653.ch64

New Scheduling Challenges

Autores: F. Reghenzani; W. Fornaciari
Publicado en: ASPDAC '23: Proceedings of the 28th Asia and South Pacific Design Automation Conference, Edición 2, 2023
Editor: ACM
DOI: 10.1145/3566097.3567851

FPGA Framework Improvements for HPC Applications

Autores: Filgueras Izquierdo, Antonio; Vidal, Miquel; Jiménez González, Daniel; Álvarez Martínez, Carlos; Martorell Bofill, Xavier
Publicado en: 2023 International Conference on Field Programmable Technology (ICFPT), Edición 1, 2024, Página(s) 286-287, ISBN 979-8-3503-5911-4
Editor: IEEE
DOI: 10.1109/icfpt59805.2023.00048

AMG Preconditioners based on Parallel Hybrid Coarsening and Multi-objective Graph Matching

Autores: Pasqua D'Ambra; Fabio Durastante; S M Ferdous; Salvatore Filippone; Mahantesh Halappanavar; Alex Pothen
Publicado en: 31st Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), Napoli, Marzo 2023, Edición 4, 2023, ISBN 979-8-3503-3763-1
Editor: IEEE
DOI: 10.1109/pdp59025.2023.00017

Dynamic Power Consumption of the Full Posit Processing Unit: Analysis and Experiments

Autores: Piccoli, Michele; Zoni, Davide; Fornaciari, William; Massari, Giuseppe; Marco, Cococcioni; Federico, Rossi; Sergio, Saponara; Emanuele, Ruffaldi
Publicado en: 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023), Edición 2, 2023
Editor: oasic
DOI: 10.4230/oasics.parma-ditam.2023.6

A Mixed-Criticality Approach to Fault Tolerance: Integrating Schedulability and Failure Requirements

Autores: Reghenzani, Federico; Zhishan, Guo; Luca, Santinelli; Fornaciari, William
Publicado en: 2022 IEEE 28th Real-Time and Embedded Technology and Applications Symposium (RTAS), 2022, Página(s) 27-39, ISBN 978-1-6654-9998-9
Editor: IEEE
DOI: 10.1109/rtas54340.2022.00011

FSP: a Framework for Data Stream Processing Applications targeting FPGAs

Autores: Albeerto Ottimo; Gabriele Mencagli; Marco Danelutto
Publicado en: Proceedings - 2023 31st Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2023, 2023, Página(s) 92-99
Editor: IEEE Press
DOI: 10.1109/pdp59025.2023.00021

Improving resource usage in large FPGA accelerators

Autores: Filgueras Izquierdo, Antonio; Alvarez, Carlos; Jiménez González, Daniel
Publicado en: 9th BSC Doctoral Symposium, 2022
Editor: BSC

MulTreePrio: Scheduling task-based applications for heterogeneous computing systems

Autores: Tayeb, Hayfa; Bramas, Bérenger; Guermouche, Abdou; Faverge, Mathieu
Publicado en: COMPAS 2022 – Conférence francophone d’informatique en Parallélisme, Architecture et Système, Edición 6, 2022
Editor: INRIA

The TEXTAROSSA Approach to Thermal Control of Future HPC Systems

Autores: William Fornaciari; Federico Terraneo; Giovanni Agosta; Zummo Giuseppe; Luca Saraceno; Giorgia Lancione; Daniele Gregori; Massimo Celino
Publicado en: Lecture Notes in Computer Science ISBN: 9783031150739, Edición 7, 2022
Editor: Springer
DOI: 10.1007/978-3-031-15074-6_27

Small Reals Representations for Deep Learning at the Edge: A Comparison

Autores: Marco Cococcioni; Federico Rossi; Emanuele Ruffaldi; Sergio Saponara
Publicado en: Conference on Next Generation Arithmetic CoNGA, Edición 5, 2022, ISBN 9783031097782
Editor: Springer
DOI: 10.1007/978-3-031-09779-9_8

On the Effectiveness of True Random Number Generators Implemented on FPGAs

Autores: Galli, Davide; Galimberti, Andrea; Fornaciari, William; Zoni, Davide
Publicado en: Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2022), Edición 4, 2022, ISBN 9783031150739
Editor: Springer
DOI: 10.1007/978-3-031-15074-6_20

Improving Performance of HPC Kernels on FPGAs Using High-Level Resource Management

Autores: Antonio Filgueras; Miquel Vidal; Daniel Jiménez-González; Carlos Álvarez; Xavier Martorell
Publicado en: 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2023, ISBN 979-8-3503-1205-8
Editor: IEEE
DOI: 10.1109/fccm57271.2023.00041

Peer reviewed articles (10)

On hardware acceleration of quantum-resistant FOTA systems in automotive

Autores: Pericle Perazzo, Stefano Di Matteo, Gianluca Dini, Sergio Saponara
Publicado en: Computers and Electrical Engineering, Edición 118, 2024, ISSN 0045-7906
Editor: Pergamon Press Ltd.
DOI: 10.1016/j.compeleceng.2024.109327

Progress report on the online processing upgrade at the NA62 experiment

Autores: M. Turisini, R. Ammendola, A. Biagioni, A. Ciardiello, P. Cretaro, O. Frezza, G. Lamanna, F. Lo Cicero, A. Lonardo, M. Martinelli, R. Piandani, D. Soldi, P. Vicini
Publicado en: Journal of Instrumentation, Edición 17480221, 2022, ISSN 1748-0221
Editor: Institute of Physics
DOI: 10.1088/1748-0221/17/04/c04002

A Survey on Run-time Power Monitors at the Edge

Autores: Davide Zoni; Andrea Galimberti; William Fornaciari
Publicado en: ACM Comput. Surv., Edición 1, 2023, Página(s) 1-33, ISSN 0360-0300
Editor: Association for Computing Machinary, Inc.
DOI: 10.1145/3593044

A Lightweight Posit Processing Unit for RISC-V Processors in Deep Neural Network Applications

Autores: Marco Cococcioni; Federico Rossi; Emanuele Ruffaldi; Sergio Saponara
Publicado en: IEEE Transactions on Emerging Topics in Computing, Edición 21686750, 2021, ISSN 2168-6750
Editor: IEEE Computer Society
DOI: 10.1109/tetc.2021.3120538

Cost-effective fixed-point hardware support for RISC-V embedded systems

Autores: D. Zoni;A. Galimberti
Publicado en: Journal of Systems Architecture, Edición 13837621, 2022, ISSN 1383-7621
Editor: Elsevier BV
DOI: 10.1016/j.sysarc.2022.102476

Parallel Sparse Computation Toolkit

Autores: Pasqua D’Ambra, Fabio Durastante, Salvatore Filippone
Publicado en: Software Impacts, Edición 15, 2023, ISSN 2665-9638
Editor: Elsevier
DOI: 10.1016/j.simpa.2022.100463

Towards EXtreme scale technologies and accelerators for euROhpc hw/Sw supercomputing applications for exascale: The TEXTAROSSA approach

Autores: Giovanni Agosta, Marco Aldinucci, Carlos Alvarez, Roberto Ammendola, Yasir Arfat, Olivier Beaumont, Massimo Bernaschi, Andrea Biagioni, Tommaso Boccali, Berenger Bramas, Carlo Brandolese, Barbara Cantalupo, Mauro Carrozzo, Daniele Cattaneo, Alessandro Celestini, Massimo Celino, Iacopo Colonnelli, Paolo Cretaro, Pasqua D’Ambra, Marco Danelutto, Roberto Esposito, Lionel Eyraud-Dubois, Antonio Filg
Publicado en: Microprocessors and Microsystems, Edición 95, 2022, ISSN 0141-9331
Editor: Elsevier BV
DOI: 10.1016/j.micpro.2022.104679

Enabling HW-Based Task Scheduling in Large Multicore Architectures

Autores: Lucas Morais; Carlos Álvarez; Daniel Jiménez-González; Juan Miguel de Haro; Guido Araujo; Michael Frank; Alfredo Goldman; Xavier Martorell
Publicado en: IEEE Transactions on Computers, Edición 18, 2024, Página(s) 138 - 151, ISSN 0018-9340
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tc.2023.3323781

A Multi-GPU Aggregation-Based AMG Preconditioner for Iterative Linear Solvers

Autores: Massimo Bernaschi; Alessandro Celestini; Flavio Vella; Pasqua D'Ambra
Publicado en: IEEE transactions on parallel and distributed systems (Online) 34 (2023): 2365–2376. doi:10.1109/TPDS.2023.3287238, Edición 3, 2023, ISSN 1045-9219
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tpds.2023.3287238

TAFFO: The compiler-based precision tuner

Autores: Daniele Cattaneo, Michele Chiari, Giovanni Agosta, Stefano Cherubin
Publicado en: SoftwareX, Edición 20, 2022, ISSN 2352-7110
Editor: Elsevier BV
DOI: 10.1016/j.softx.2022.101238