Digital Autonomy for RISC-V in Europe (Specific Grant Agreement 1)

Project Information

DARE SGA 1

Grant agreement ID: 101202459

DOI

10.3030/101202459

EC signature date 18 February 2025

Start date 1 March 2025

End date 29 February 2028

Funded under

• Digital, Industry and Space

Total cost

€ 239 995 859,50

EU contribution

€ 102 262 283,43

Coordinated by

BARCELONA SUPERCOMPUTING CENTER CENTRO NACIONAL DE SUPERCOMPUTACION
Spain

CORDIS provides links to public deliverables and publications of HORIZON projects.

Links to deliverables and publications from FP7 projects, as well as links to some specific result types such as dataset and software, are dynamically retrieved from OpenAIRE .

Deliverables

Documents, reports (4)

Data management plan

DMP

Communication and Dissemination Plan

Description of the communication and dissemination strategy, the activities to be undertaken to achieve this, and KPIs to monitor progress. Dissemination results will be reported in the periodic and final reports.

Off-the-shelf RISC-V SDV User Documentation
Functional Emulator SDV User Documentation

Publications

Other (1)

Report on Maturity of LLVM's Fortran Support

Author(s): Toda, Ferran; Ferrer, Roger
Published in: 2025
Publisher: Zenodo
DOI: 10.5281/ZENODO.16960275

Conference proceedings (4)

Sisyphus: Cross-Layer Efficiency Across NVM Technologies in Compute-in-Memory Architectures

Author(s): Ali Nezhadi, Odysseas Chatzopoulos, Mahta Mayahinia, George Papadimitriou, Mehdi Tahoori, Dimitris Gizopoulos
Published in: 2025 IEEE International Test Conference (ITC), 2025
Publisher: IEEE
DOI: 10.1109/ITC58126.2025.00028

Evaluating ECC for Cache Reliability Under Multi-Bit Upsets: A Design Space Exploration

Author(s): Foteini Kotsimpou, George Papadimitriou, Dimitris Gizopoulos
Published in: 2025 IEEE 31st International Symposium on On-Line Testing and Robust System Design (IOLTS), 2025
Publisher: IEEE
DOI: 10.1109/IOLTS65288.2025.11117031

Accurate Analysis of Silent Data Corruptions in Programmable AI Accelerator Microarchitectures

Author(s): Odysseas Chatzopoulos, Maria Trakosa, Dimitris Gizopoulos
Published in: 2025 IEEE 31st International Symposium on On-Line Testing and Robust System Design (IOLTS), 2025
Publisher: IEEE
DOI: 10.1109/IOLTS65288.2025.11117132

vACE: Exploring the Design Space of Vector Processing Units for Soft Error Vulnerability

Author(s): George-Marios Fragkoulis, Dimitris Gizopoulos
Published in: 2025 IEEE International Symposium on Workload Characterization (IISWC), 2025
Publisher: IEEE
DOI: 10.1109/IISWC66894.2025.00023

Peer reviewed articles (3)

Towards RISC-V-based HPC: The Italian Pathfinding Activities in the DARE-SGA1 Project

Author(s): Agosta G.; Aldinucci M.; Bartolini A.; Bellentani L.; Biagioni A.; Cesarini D.; Chiarini C.; Colonnelli I.; Delugas P.; Denisov L.; Frezza O.; Grangetto M.; Cicero F. L.; Lonardo A.; Martinelli M.; Maslov A.; Olivieri M.; Perticaroli P.; Pontisso L.; Rossi C.; Rossi D.; Saponara S.; Sciarappa A.; Simula F.; Reorda M. S.; Torquati M.; Vicini P.
Published in: 2025 28th Euromicro Conference on Digital System Design (DSD), 2026, ISSN 2771-2508
Publisher: IEEE
DOI: 10.1109/DSD67783.2025.00057

Harpocrates++: Automated Functional Program Generation Against CPU Faults and Silent Data Corruptions

Author(s): Nikos Karystinos, George-Marios Fragkoulis, Odysseas Chatzopoulos, Dimitris Gizopoulos, Sudhanva Gurumurthi
Published in: IEEE Micro, Issue 46, 2026, ISSN 0272-1732
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
DOI: 10.1109/MM.2025.3640385

Phoebe: Measuring the Unmeasurable—Demystifying Silent Data Corruptions in AI Accelerators Through Microarchitectural Modeling

Author(s): Odysseas Chatzopoulos, Maria Trakosa, Harish D. Dixit, Sriram Sankar, Dimitris Gizopoulos
Published in: IEEE Micro, Issue 46, 2026, ISSN 0272-1732
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
DOI: 10.1109/MM.2025.3646859